libmultipath: nvme: update to nvme-cli v1.9
[multipath-tools/.git] / libmultipath / nvme / linux / nvme.h
1 /*
2  * Definitions for the NVM Express interface
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <linux/types.h>
19 #include <linux/uuid.h>
20
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN      256
23
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE           223
26
27 #define NVMF_TRSVCID_SIZE       32
28 #define NVMF_TRADDR_SIZE        256
29 #define NVMF_TSAS_SIZE          256
30
31 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
32
33 #define NVME_RDMA_IP_PORT       4420
34
35 #define NVME_NSID_ALL           0xffffffff
36
37 enum nvme_subsys_type {
38         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
39         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
40 };
41
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
43 enum {
44         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
45         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
46         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
47         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
48         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
49 };
50
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
52 enum {
53         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
54         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
55         NVMF_TRTYPE_TCP         = 3,    /* TCP */
56         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
57         NVMF_TRTYPE_MAX,
58 };
59
60 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
61 enum {
62         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
63         NVMF_TREQ_REQUIRED      = 1,            /* Required */
64         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
65         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* SQ flow control disable supported */
66 };
67
68 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
69  * RDMA_QPTYPE field
70  */
71 enum {
72         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
73         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
74 };
75
76 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
77  * RDMA_QPTYPE field
78  */
79 enum {
80         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
81         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
82         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
83         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
84         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
85 };
86
87 /* RDMA Connection Management Service Type codes for Discovery Log Page
88  * entry TSAS RDMA_CMS field
89  */
90 enum {
91         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
92 };
93
94 /* TCP port security type for  Discovery Log Page entry TSAS
95  */
96 enum {
97         NVMF_TCP_SECTYPE_NONE   = 0, /* No Security */
98         NVMF_TCP_SECTYPE_TLS    = 1, /* Transport Layer Security */
99 };
100
101 #define NVME_AQ_DEPTH           32
102 #define NVME_NR_AEN_COMMANDS    1
103 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
104
105 /*
106  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
107  * NVM-Express 1.2 specification, section 4.1.2.
108  */
109 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
110
111 enum {
112         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
113         NVME_REG_VS     = 0x0008,       /* Version */
114         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
115         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
116         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
117         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
118         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
119         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
120         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
121         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
122         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
123         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
124         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
125         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
126         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer Location */
127         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
128         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
129         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
130         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
131 };
132
133 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
134 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
135 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
136 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
137 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
138 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
139
140 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
141 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
142 #define NVME_CMB_SZ(cmbsz)      (((cmbsz) >> 12) & 0xfffff)
143 #define NVME_CMB_SZU(cmbsz)     (((cmbsz) >> 8) & 0xf)
144
145 #define NVME_CMB_WDS(cmbsz)     ((cmbsz) & 0x10)
146 #define NVME_CMB_RDS(cmbsz)     ((cmbsz) & 0x8)
147 #define NVME_CMB_LISTS(cmbsz)   ((cmbsz) & 0x4)
148 #define NVME_CMB_CQS(cmbsz)     ((cmbsz) & 0x2)
149 #define NVME_CMB_SQS(cmbsz)     ((cmbsz) & 0x1)
150
151 /*
152  * Submission and Completion Queue Entry Sizes for the NVM command set.
153  * (In bytes and specified as a power of two (2^n)).
154  */
155 #define NVME_NVM_IOSQES         6
156 #define NVME_NVM_IOCQES         4
157
158 enum {
159         NVME_CC_ENABLE          = 1 << 0,
160         NVME_CC_CSS_NVM         = 0 << 4,
161         NVME_CC_EN_SHIFT        = 0,
162         NVME_CC_CSS_SHIFT       = 4,
163         NVME_CC_MPS_SHIFT       = 7,
164         NVME_CC_AMS_SHIFT       = 11,
165         NVME_CC_SHN_SHIFT       = 14,
166         NVME_CC_IOSQES_SHIFT    = 16,
167         NVME_CC_IOCQES_SHIFT    = 20,
168         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
169         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
170         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
171         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
172         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
173         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
174         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
175         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
176         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
177         NVME_CSTS_RDY           = 1 << 0,
178         NVME_CSTS_CFS           = 1 << 1,
179         NVME_CSTS_NSSRO         = 1 << 4,
180         NVME_CSTS_PP            = 1 << 5,
181         NVME_CSTS_SHST_NORMAL   = 0 << 2,
182         NVME_CSTS_SHST_OCCUR    = 1 << 2,
183         NVME_CSTS_SHST_CMPLT    = 2 << 2,
184         NVME_CSTS_SHST_MASK     = 3 << 2,
185 };
186
187 struct nvme_id_power_state {
188         __le16                  max_power;      /* centiwatts */
189         __u8                    rsvd2;
190         __u8                    flags;
191         __le32                  entry_lat;      /* microseconds */
192         __le32                  exit_lat;       /* microseconds */
193         __u8                    read_tput;
194         __u8                    read_lat;
195         __u8                    write_tput;
196         __u8                    write_lat;
197         __le16                  idle_power;
198         __u8                    idle_scale;
199         __u8                    rsvd19;
200         __le16                  active_power;
201         __u8                    active_work_scale;
202         __u8                    rsvd23[9];
203 };
204
205 enum {
206         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
207         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
208 };
209
210 struct nvme_id_ctrl {
211         __le16                  vid;
212         __le16                  ssvid;
213         char                    sn[20];
214         char                    mn[40];
215         char                    fr[8];
216         __u8                    rab;
217         __u8                    ieee[3];
218         __u8                    cmic;
219         __u8                    mdts;
220         __le16                  cntlid;
221         __le32                  ver;
222         __le32                  rtd3r;
223         __le32                  rtd3e;
224         __le32                  oaes;
225         __le32                  ctratt;
226         __le16                  rrls;
227         __u8                    rsvd102[26];
228         __le16                  crdt1;
229         __le16                  crdt2;
230         __le16                  crdt3;
231         __u8                    rsvd134[122];
232         __le16                  oacs;
233         __u8                    acl;
234         __u8                    aerl;
235         __u8                    frmw;
236         __u8                    lpa;
237         __u8                    elpe;
238         __u8                    npss;
239         __u8                    avscc;
240         __u8                    apsta;
241         __le16                  wctemp;
242         __le16                  cctemp;
243         __le16                  mtfa;
244         __le32                  hmpre;
245         __le32                  hmmin;
246         __u8                    tnvmcap[16];
247         __u8                    unvmcap[16];
248         __le32                  rpmbs;
249         __le16                  edstt;
250         __u8                    dsto;
251         __u8                    fwug;
252         __le16                  kas;
253         __le16                  hctma;
254         __le16                  mntmt;
255         __le16                  mxtmt;
256         __le32                  sanicap;
257         __le32                  hmminds;
258         __le16                  hmmaxd;
259         __le16                  nsetidmax;
260         __u8                    rsvd340[2];
261         __u8                    anatt;
262         __u8                    anacap;
263         __le32                  anagrpmax;
264         __le32                  nanagrpid;
265         __u8                    rsvd352[160];
266         __u8                    sqes;
267         __u8                    cqes;
268         __le16                  maxcmd;
269         __le32                  nn;
270         __le16                  oncs;
271         __le16                  fuses;
272         __u8                    fna;
273         __u8                    vwc;
274         __le16                  awun;
275         __le16                  awupf;
276         __u8                    nvscc;
277         __u8                    nwpc;
278         __le16                  acwu;
279         __u8                    rsvd534[2];
280         __le32                  sgls;
281         __le32                  mnan;
282         __u8                    rsvd544[224];
283         char                    subnqn[256];
284         __u8                    rsvd1024[768];
285         __le32                  ioccsz;
286         __le32                  iorcsz;
287         __le16                  icdoff;
288         __u8                    ctrattr;
289         __u8                    msdbd;
290         __u8                    rsvd1804[244];
291         struct nvme_id_power_state      psd[32];
292         __u8                    vs[1024];
293 };
294
295 enum {
296         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
297         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
298         NVME_CTRL_ONCS_DSM                      = 1 << 2,
299         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
300         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
301         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
302         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
303         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
304         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
305         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
306         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
307         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
308         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
309         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
310         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
311         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
312         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
313         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
314 };
315
316 struct nvme_lbaf {
317         __le16                  ms;
318         __u8                    ds;
319         __u8                    rp;
320 };
321
322 struct nvme_id_ns {
323         __le64                  nsze;
324         __le64                  ncap;
325         __le64                  nuse;
326         __u8                    nsfeat;
327         __u8                    nlbaf;
328         __u8                    flbas;
329         __u8                    mc;
330         __u8                    dpc;
331         __u8                    dps;
332         __u8                    nmic;
333         __u8                    rescap;
334         __u8                    fpi;
335         __u8                    dlfeat;
336         __le16                  nawun;
337         __le16                  nawupf;
338         __le16                  nacwu;
339         __le16                  nabsn;
340         __le16                  nabo;
341         __le16                  nabspf;
342         __le16                  noiob;
343         __u8                    nvmcap[16];
344         __le16                  npwg;
345         __le16                  npwa;
346         __le16                  npdg;
347         __le16                  npda;
348         __le16                  nows;
349         __u8                    rsvd74[18];
350         __le32                  anagrpid;
351         __u8                    rsvd96[3];
352         __u8                    nsattr;
353         __le16                  nvmsetid;
354         __le16                  endgid;
355         __u8                    nguid[16];
356         __u8                    eui64[8];
357         struct nvme_lbaf        lbaf[16];
358         __u8                    rsvd192[192];
359         __u8                    vs[3712];
360 };
361
362 enum {
363         NVME_ID_CNS_NS                  = 0x00,
364         NVME_ID_CNS_CTRL                = 0x01,
365         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
366         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
367         NVME_ID_CNS_NVMSET_LIST         = 0x04,
368         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
369         NVME_ID_CNS_NS_PRESENT          = 0x11,
370         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
371         NVME_ID_CNS_CTRL_LIST           = 0x13,
372         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
373         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
374         NVME_ID_CNS_UUID_LIST           = 0x17,
375 };
376
377 enum {
378         NVME_DIR_IDENTIFY               = 0x00,
379         NVME_DIR_STREAMS                = 0x01,
380         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
381         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
382         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
383         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
384         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
385         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
386         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
387         NVME_DIR_ENDIR                  = 0x01,
388 };
389
390 enum {
391         NVME_NS_FEAT_THIN       = 1 << 0,
392         NVME_NS_FLBAS_LBA_MASK  = 0xf,
393         NVME_NS_FLBAS_META_EXT  = 0x10,
394         NVME_LBAF_RP_BEST       = 0,
395         NVME_LBAF_RP_BETTER     = 1,
396         NVME_LBAF_RP_GOOD       = 2,
397         NVME_LBAF_RP_DEGRADED   = 3,
398         NVME_NS_DPC_PI_LAST     = 1 << 4,
399         NVME_NS_DPC_PI_FIRST    = 1 << 3,
400         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
401         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
402         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
403         NVME_NS_DPS_PI_FIRST    = 1 << 3,
404         NVME_NS_DPS_PI_MASK     = 0x7,
405         NVME_NS_DPS_PI_TYPE1    = 1,
406         NVME_NS_DPS_PI_TYPE2    = 2,
407         NVME_NS_DPS_PI_TYPE3    = 3,
408 };
409
410 struct nvme_ns_id_desc {
411         __u8 nidt;
412         __u8 nidl;
413         __le16 reserved;
414 };
415
416 #define NVME_NIDT_EUI64_LEN     8
417 #define NVME_NIDT_NGUID_LEN     16
418 #define NVME_NIDT_UUID_LEN      16
419
420 enum {
421         NVME_NIDT_EUI64         = 0x01,
422         NVME_NIDT_NGUID         = 0x02,
423         NVME_NIDT_UUID          = 0x03,
424 };
425
426 #define NVME_MAX_NVMSET         31
427
428 struct nvme_nvmset_attr_entry {
429         __le16                  id;
430         __le16                  endurance_group_id;
431         __u8                    rsvd4[4];
432         __le32                  random_4k_read_typical;
433         __le32                  opt_write_size;
434         __u8                    total_nvmset_cap[16];
435         __u8                    unalloc_nvmset_cap[16];
436         __u8                    rsvd48[80];
437 };
438
439 struct nvme_id_nvmset {
440         __u8                            nid;
441         __u8                            rsvd1[127];
442         struct nvme_nvmset_attr_entry   ent[NVME_MAX_NVMSET];
443 };
444
445 struct nvme_id_ns_granularity_list_entry {
446         __le64                  namespace_size_granularity;
447         __le64                  namespace_capacity_granularity;
448 };
449
450 struct nvme_id_ns_granularity_list {
451         __le32                  attributes;
452         __u8                    num_descriptors;
453         __u8                    rsvd[27];
454         struct nvme_id_ns_granularity_list_entry entry[16];
455 };
456
457 #define NVME_MAX_UUID_ENTRIES   128
458 struct nvme_id_uuid_list_entry {
459         __u8                    header;
460         __u8                    rsvd1[15];
461         __u8                    uuid[16];
462 };
463
464 struct nvme_id_uuid_list {
465         struct nvme_id_uuid_list_entry  entry[NVME_MAX_UUID_ENTRIES];
466 };
467
468 /**
469  * struct nvme_telemetry_log_page_hdr - structure for telemetry log page
470  * @lpi: Log page identifier
471  * @iee_oui: IEEE OUI Identifier
472  * @dalb1: Data area 1 last block
473  * @dalb2: Data area 2 last block
474  * @dalb3: Data area 3 last block
475  * @ctrlavail: Controller initiated data available
476  * @ctrldgn: Controller initiated telemetry Data Generation Number
477  * @rsnident: Reason Identifier
478  * @telemetry_dataarea: Contains telemetry data block
479  *
480  * This structure can be used for both telemetry host-initiated log page
481  * and controller-initiated log page.
482  */
483 struct nvme_telemetry_log_page_hdr {
484         __u8    lpi;
485         __u8    rsvd[4];
486         __u8    iee_oui[3];
487         __le16  dalb1;
488         __le16  dalb2;
489         __le16  dalb3;
490         __u8    rsvd1[368];
491         __u8    ctrlavail;
492         __u8    ctrldgn;
493         __u8    rsnident[128];
494         __u8    telemetry_dataarea[0];
495 };
496
497 struct nvme_endurance_group_log {
498         __u32   rsvd0;
499         __u8    avl_spare_threshold;
500         __u8    percent_used;
501         __u8    rsvd6[26];
502         __u8    endurance_estimate[16];
503         __u8    data_units_read[16];
504         __u8    data_units_written[16];
505         __u8    media_units_written[16];
506         __u8    rsvd96[416];
507 };
508
509 struct nvme_smart_log {
510         __u8                    critical_warning;
511         __u8                    temperature[2];
512         __u8                    avail_spare;
513         __u8                    spare_thresh;
514         __u8                    percent_used;
515         __u8                    rsvd6[26];
516         __u8                    data_units_read[16];
517         __u8                    data_units_written[16];
518         __u8                    host_reads[16];
519         __u8                    host_writes[16];
520         __u8                    ctrl_busy_time[16];
521         __u8                    power_cycles[16];
522         __u8                    power_on_hours[16];
523         __u8                    unsafe_shutdowns[16];
524         __u8                    media_errors[16];
525         __u8                    num_err_log_entries[16];
526         __le32                  warning_temp_time;
527         __le32                  critical_comp_time;
528         __le16                  temp_sensor[8];
529         __le32                  thm_temp1_trans_count;
530         __le32                  thm_temp2_trans_count;
531         __le32                  thm_temp1_total_time;
532         __le32                  thm_temp2_total_time;
533         __u8                    rsvd232[280];
534 };
535
536 struct nvme_self_test_res {
537         __u8                    device_self_test_status;
538         __u8                    segment_num;
539         __u8                    valid_diagnostic_info;
540         __u8                    rsvd;
541         __le64                  power_on_hours;
542         __le32                  nsid;
543         __le64                  failing_lba;
544         __u8                    status_code_type;
545         __u8                    status_code;
546         __u8                    vendor_specific[2];
547 } __attribute__((packed));
548
549 struct nvme_self_test_log {
550         __u8                      crnt_dev_selftest_oprn;
551         __u8                      crnt_dev_selftest_compln;
552         __u8                      rsvd[2];
553         struct nvme_self_test_res result[20];
554 } __attribute__((packed));
555
556 struct nvme_fw_slot_info_log {
557         __u8                    afi;
558         __u8                    rsvd1[7];
559         __le64                  frs[7];
560         __u8                    rsvd64[448];
561 };
562
563 struct nvme_lba_status_desc {
564         __u64 dslba;
565         __u32 nlb;
566         __u8 rsvd_12;
567         __u8 status;
568         __u8 rsvd_15_14[2];
569 };
570
571 struct nvme_lba_status {
572         __u32 nlsd;
573         __u8 cmpc;
574         __u8 rsvd_7_5[3];
575         struct nvme_lba_status_desc descs[0];
576 };
577
578 /* NVMe Namespace Write Protect State */
579 enum {
580         NVME_NS_NO_WRITE_PROTECT = 0,
581         NVME_NS_WRITE_PROTECT,
582         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
583         NVME_NS_WRITE_PROTECT_PERMANENT,
584 };
585
586 #define NVME_MAX_CHANGED_NAMESPACES     1024
587
588 struct nvme_changed_ns_list_log {
589         __le32                  log[NVME_MAX_CHANGED_NAMESPACES];
590 };
591
592 enum {
593         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
594         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
595         NVME_CMD_EFFECTS_NCC            = 1 << 2,
596         NVME_CMD_EFFECTS_NIC            = 1 << 3,
597         NVME_CMD_EFFECTS_CCC            = 1 << 4,
598         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
599         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
600 };
601
602 struct nvme_effects_log {
603         __le32 acs[256];
604         __le32 iocs[256];
605         __u8   resv[2048];
606 };
607
608 enum nvme_ana_state {
609         NVME_ANA_OPTIMIZED              = 0x01,
610         NVME_ANA_NONOPTIMIZED           = 0x02,
611         NVME_ANA_INACCESSIBLE           = 0x03,
612         NVME_ANA_PERSISTENT_LOSS        = 0x04,
613         NVME_ANA_CHANGE                 = 0x0f,
614 };
615
616 struct nvme_ana_group_desc {
617         __le32  grpid;
618         __le32  nnsids;
619         __le64  chgcnt;
620         __u8    state;
621         __u8    rsvd17[15];
622         __le32  nsids[];
623 };
624
625 /* flag for the log specific field of the ANA log */
626 #define NVME_ANA_LOG_RGO   (1 << 0)
627
628 struct nvme_ana_rsp_hdr {
629         __le64  chgcnt;
630         __le16  ngrps;
631         __le16  rsvd10[3];
632 };
633
634 enum {
635         NVME_SMART_CRIT_SPARE           = 1 << 0,
636         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
637         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
638         NVME_SMART_CRIT_MEDIA           = 1 << 3,
639         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
640 };
641
642 enum {
643         NVME_AER_ERROR                  = 0,
644         NVME_AER_SMART                  = 1,
645         NVME_AER_CSS                    = 6,
646         NVME_AER_VS                     = 7,
647 };
648
649 struct nvme_lba_range_type {
650         __u8                    type;
651         __u8                    attributes;
652         __u8                    rsvd2[14];
653         __u64                   slba;
654         __u64                   nlb;
655         __u8                    guid[16];
656         __u8                    rsvd48[16];
657 };
658
659 enum {
660         NVME_LBART_TYPE_FS      = 0x01,
661         NVME_LBART_TYPE_RAID    = 0x02,
662         NVME_LBART_TYPE_CACHE   = 0x03,
663         NVME_LBART_TYPE_SWAP    = 0x04,
664
665         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
666         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
667 };
668
669 /* Predictable Latency Mode - Deterministic Threshold Configuration Data */
670 struct nvme_plm_config {
671         __le16  enable_event;
672         __u8    rsvd2[30];
673         __le64  dtwin_reads_thresh;
674         __le64  dtwin_writes_thresh;
675         __le64  dtwin_time_thresh;
676         __u8    rsvd56[456];
677 };
678
679 struct nvme_reservation_status {
680         __le32  gen;
681         __u8    rtype;
682         __u8    regctl[2];
683         __u8    resv5[2];
684         __u8    ptpls;
685         __u8    resv10[13];
686         struct {
687                 __le16  cntlid;
688                 __u8    rcsts;
689                 __u8    resv3[5];
690                 __le64  hostid;
691                 __le64  rkey;
692         } regctl_ds[];
693 };
694
695 struct nvme_reservation_status_ext {
696         __le32  gen;
697         __u8    rtype;
698         __u8    regctl[2];
699         __u8    resv5[2];
700         __u8    ptpls;
701         __u8    resv10[14];
702         __u8    resv24[40];
703         struct {
704                 __le16  cntlid;
705                 __u8    rcsts;
706                 __u8    resv3[5];
707                 __le64  rkey;
708                 __u8    hostid[16];
709                 __u8    resv32[32];
710         } regctl_eds[];
711 };
712
713 enum nvme_async_event_type {
714         NVME_AER_TYPE_ERROR     = 0,
715         NVME_AER_TYPE_SMART     = 1,
716         NVME_AER_TYPE_NOTICE    = 2,
717 };
718
719 /* I/O commands */
720
721 enum nvme_opcode {
722         nvme_cmd_flush          = 0x00,
723         nvme_cmd_write          = 0x01,
724         nvme_cmd_read           = 0x02,
725         nvme_cmd_write_uncor    = 0x04,
726         nvme_cmd_compare        = 0x05,
727         nvme_cmd_write_zeroes   = 0x08,
728         nvme_cmd_dsm            = 0x09,
729         nvme_cmd_verify         = 0x0c,
730         nvme_cmd_resv_register  = 0x0d,
731         nvme_cmd_resv_report    = 0x0e,
732         nvme_cmd_resv_acquire   = 0x11,
733         nvme_cmd_resv_release   = 0x15,
734 };
735
736 /*
737  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
738  *
739  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
740  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
741  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
742  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
743  *                            request subtype
744  */
745 enum {
746         NVME_SGL_FMT_ADDRESS            = 0x00,
747         NVME_SGL_FMT_OFFSET             = 0x01,
748         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
749         NVME_SGL_FMT_INVALIDATE         = 0x0f,
750 };
751
752 /*
753  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
754  *
755  * For struct nvme_sgl_desc:
756  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
757  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
758  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
759  *
760  * For struct nvme_keyed_sgl_desc:
761  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
762  *
763  * Transport-specific SGL types:
764  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
765  */
766 enum {
767         NVME_SGL_FMT_DATA_DESC          = 0x00,
768         NVME_SGL_FMT_SEG_DESC           = 0x02,
769         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
770         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
771         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
772 };
773
774 struct nvme_sgl_desc {
775         __le64  addr;
776         __le32  length;
777         __u8    rsvd[3];
778         __u8    type;
779 };
780
781 struct nvme_keyed_sgl_desc {
782         __le64  addr;
783         __u8    length[3];
784         __u8    key[4];
785         __u8    type;
786 };
787
788 union nvme_data_ptr {
789         struct {
790                 __le64  prp1;
791                 __le64  prp2;
792         };
793         struct nvme_sgl_desc    sgl;
794         struct nvme_keyed_sgl_desc ksgl;
795 };
796
797 /*
798  * Lowest two bits of our flags field (FUSE field in the spec):
799  *
800  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
801  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
802  *
803  * Highest two bits in our flags field (PSDT field in the spec):
804  *
805  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
806  *      If used, MPTR contains addr of single physical buffer (byte aligned).
807  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
808  *      If used, MPTR contains an address of an SGL segment containing
809  *      exactly 1 SGL descriptor (qword aligned).
810  */
811 enum {
812         NVME_CMD_FUSE_FIRST     = (1 << 0),
813         NVME_CMD_FUSE_SECOND    = (1 << 1),
814
815         NVME_CMD_SGL_METABUF    = (1 << 6),
816         NVME_CMD_SGL_METASEG    = (1 << 7),
817         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
818 };
819
820 struct nvme_common_command {
821         __u8                    opcode;
822         __u8                    flags;
823         __u16                   command_id;
824         __le32                  nsid;
825         __le32                  cdw2[2];
826         __le64                  metadata;
827         union nvme_data_ptr     dptr;
828         __le32                  cdw10[6];
829 };
830
831 struct nvme_rw_command {
832         __u8                    opcode;
833         __u8                    flags;
834         __u16                   command_id;
835         __le32                  nsid;
836         __u64                   rsvd2;
837         __le64                  metadata;
838         union nvme_data_ptr     dptr;
839         __le64                  slba;
840         __le16                  length;
841         __le16                  control;
842         __le32                  dsmgmt;
843         __le32                  reftag;
844         __le16                  apptag;
845         __le16                  appmask;
846 };
847
848 enum {
849         NVME_RW_LR                      = 1 << 15,
850         NVME_RW_FUA                     = 1 << 14,
851         NVME_RW_DEAC                    = 1 << 9,
852         NVME_RW_DSM_FREQ_UNSPEC         = 0,
853         NVME_RW_DSM_FREQ_TYPICAL        = 1,
854         NVME_RW_DSM_FREQ_RARE           = 2,
855         NVME_RW_DSM_FREQ_READS          = 3,
856         NVME_RW_DSM_FREQ_WRITES         = 4,
857         NVME_RW_DSM_FREQ_RW             = 5,
858         NVME_RW_DSM_FREQ_ONCE           = 6,
859         NVME_RW_DSM_FREQ_PREFETCH       = 7,
860         NVME_RW_DSM_FREQ_TEMP           = 8,
861         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
862         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
863         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
864         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
865         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
866         NVME_RW_DSM_COMPRESSED          = 1 << 7,
867         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
868         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
869         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
870         NVME_RW_PRINFO_PRACT            = 1 << 13,
871         NVME_RW_DTYPE_STREAMS           = 1 << 4,
872 };
873
874 struct nvme_dsm_cmd {
875         __u8                    opcode;
876         __u8                    flags;
877         __u16                   command_id;
878         __le32                  nsid;
879         __u64                   rsvd2[2];
880         union nvme_data_ptr     dptr;
881         __le32                  nr;
882         __le32                  attributes;
883         __u32                   rsvd12[4];
884 };
885
886 enum {
887         NVME_DSMGMT_IDR         = 1 << 0,
888         NVME_DSMGMT_IDW         = 1 << 1,
889         NVME_DSMGMT_AD          = 1 << 2,
890 };
891
892 #define NVME_DSM_MAX_RANGES     256
893
894 struct nvme_dsm_range {
895         __le32                  cattr;
896         __le32                  nlb;
897         __le64                  slba;
898 };
899
900 struct nvme_write_zeroes_cmd {
901         __u8                    opcode;
902         __u8                    flags;
903         __u16                   command_id;
904         __le32                  nsid;
905         __u64                   rsvd2;
906         __le64                  metadata;
907         union nvme_data_ptr     dptr;
908         __le64                  slba;
909         __le16                  length;
910         __le16                  control;
911         __le32                  dsmgmt;
912         __le32                  reftag;
913         __le16                  apptag;
914         __le16                  appmask;
915 };
916
917 /* Features */
918
919 struct nvme_feat_auto_pst {
920         __le64 entries[32];
921 };
922
923 enum {
924         NVME_HOST_MEM_ENABLE    = (1 << 0),
925         NVME_HOST_MEM_RETURN    = (1 << 1),
926 };
927
928 /* Admin commands */
929
930 enum nvme_admin_opcode {
931         nvme_admin_delete_sq            = 0x00,
932         nvme_admin_create_sq            = 0x01,
933         nvme_admin_get_log_page         = 0x02,
934         nvme_admin_delete_cq            = 0x04,
935         nvme_admin_create_cq            = 0x05,
936         nvme_admin_identify             = 0x06,
937         nvme_admin_abort_cmd            = 0x08,
938         nvme_admin_set_features         = 0x09,
939         nvme_admin_get_features         = 0x0a,
940         nvme_admin_async_event          = 0x0c,
941         nvme_admin_ns_mgmt              = 0x0d,
942         nvme_admin_activate_fw          = 0x10,
943         nvme_admin_download_fw          = 0x11,
944         nvme_admin_dev_self_test        = 0x14,
945         nvme_admin_ns_attach            = 0x15,
946         nvme_admin_keep_alive           = 0x18,
947         nvme_admin_directive_send       = 0x19,
948         nvme_admin_directive_recv       = 0x1a,
949         nvme_admin_virtual_mgmt         = 0x1c,
950         nvme_admin_nvme_mi_send         = 0x1d,
951         nvme_admin_nvme_mi_recv         = 0x1e,
952         nvme_admin_dbbuf                = 0x7C,
953         nvme_admin_format_nvm           = 0x80,
954         nvme_admin_security_send        = 0x81,
955         nvme_admin_security_recv        = 0x82,
956         nvme_admin_sanitize_nvm         = 0x84,
957         nvme_admin_get_lba_status       = 0x86,
958 };
959
960 enum {
961         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
962         NVME_CQ_IRQ_ENABLED     = (1 << 1),
963         NVME_SQ_PRIO_URGENT     = (0 << 1),
964         NVME_SQ_PRIO_HIGH       = (1 << 1),
965         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
966         NVME_SQ_PRIO_LOW        = (3 << 1),
967         NVME_FEAT_ARBITRATION   = 0x01,
968         NVME_FEAT_POWER_MGMT    = 0x02,
969         NVME_FEAT_LBA_RANGE     = 0x03,
970         NVME_FEAT_TEMP_THRESH   = 0x04,
971         NVME_FEAT_ERR_RECOVERY  = 0x05,
972         NVME_FEAT_VOLATILE_WC   = 0x06,
973         NVME_FEAT_NUM_QUEUES    = 0x07,
974         NVME_FEAT_IRQ_COALESCE  = 0x08,
975         NVME_FEAT_IRQ_CONFIG    = 0x09,
976         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
977         NVME_FEAT_ASYNC_EVENT   = 0x0b,
978         NVME_FEAT_AUTO_PST      = 0x0c,
979         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
980         NVME_FEAT_TIMESTAMP     = 0x0e,
981         NVME_FEAT_KATO          = 0x0f,
982         NVME_FEAT_HCTM          = 0X10,
983         NVME_FEAT_NOPSC         = 0X11,
984         NVME_FEAT_RRL           = 0x12,
985         NVME_FEAT_PLM_CONFIG    = 0x13,
986         NVME_FEAT_PLM_WINDOW    = 0x14,
987         NVME_FEAT_HOST_BEHAVIOR = 0x16,
988         NVME_FEAT_SANITIZE      = 0x17,
989         NVME_FEAT_SW_PROGRESS   = 0x80,
990         NVME_FEAT_HOST_ID       = 0x81,
991         NVME_FEAT_RESV_MASK     = 0x82,
992         NVME_FEAT_RESV_PERSIST  = 0x83,
993         NVME_FEAT_WRITE_PROTECT = 0x84,
994         NVME_LOG_ERROR          = 0x01,
995         NVME_LOG_SMART          = 0x02,
996         NVME_LOG_FW_SLOT        = 0x03,
997         NVME_LOG_CHANGED_NS     = 0x04,
998         NVME_LOG_CMD_EFFECTS    = 0x05,
999         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1000         NVME_LOG_TELEMETRY_HOST = 0x07,
1001         NVME_LOG_TELEMETRY_CTRL = 0x08,
1002         NVME_LOG_ENDURANCE_GROUP = 0x09,
1003         NVME_LOG_ANA            = 0x0c,
1004         NVME_LOG_DISC           = 0x70,
1005         NVME_LOG_RESERVATION    = 0x80,
1006         NVME_LOG_SANITIZE       = 0x81,
1007         NVME_FWACT_REPL         = (0 << 3),
1008         NVME_FWACT_REPL_ACTV    = (1 << 3),
1009         NVME_FWACT_ACTV         = (2 << 3),
1010 };
1011
1012 enum {
1013         NVME_NO_LOG_LSP       = 0x0,
1014         NVME_NO_LOG_LPO       = 0x0,
1015         NVME_LOG_ANA_LSP_RGO  = 0x1,
1016         NVME_TELEM_LSP_CREATE = 0x1,
1017 };
1018
1019 /* Sanitize and Sanitize Monitor/Log */
1020 enum {
1021         /* Sanitize */
1022         NVME_SANITIZE_NO_DEALLOC        = 0x00000200,
1023         NVME_SANITIZE_OIPBP             = 0x00000100,
1024         NVME_SANITIZE_OWPASS_SHIFT      = 0x00000004,
1025         NVME_SANITIZE_AUSE              = 0x00000008,
1026         NVME_SANITIZE_ACT_CRYPTO_ERASE  = 0x00000004,
1027         NVME_SANITIZE_ACT_OVERWRITE     = 0x00000003,
1028         NVME_SANITIZE_ACT_BLOCK_ERASE   = 0x00000002,
1029         NVME_SANITIZE_ACT_EXIT          = 0x00000001,
1030
1031         /* Sanitize Monitor/Log */
1032         NVME_SANITIZE_LOG_DATA_LEN              = 0x0014,
1033         NVME_SANITIZE_LOG_GLOBAL_DATA_ERASED    = 0x0100,
1034         NVME_SANITIZE_LOG_NUM_CMPLTED_PASS_MASK = 0x00F8,
1035         NVME_SANITIZE_LOG_STATUS_MASK           = 0x0007,
1036         NVME_SANITIZE_LOG_NEVER_SANITIZED       = 0x0000,
1037         NVME_SANITIZE_LOG_COMPLETED_SUCCESS     = 0x0001,
1038         NVME_SANITIZE_LOG_IN_PROGESS            = 0x0002,
1039         NVME_SANITIZE_LOG_COMPLETED_FAILED      = 0x0003,
1040         NVME_SANITIZE_LOG_ND_COMPLETED_SUCCESS  = 0x0004,
1041 };
1042
1043 enum {
1044         /* Self-test log Validation bits */
1045         NVME_SELF_TEST_VALID_NSID       = 1 << 0,
1046         NVME_SELF_TEST_VALID_FLBA       = 1 << 1,
1047         NVME_SELF_TEST_VALID_SCT        = 1 << 2,
1048         NVME_SELF_TEST_VALID_SC         = 1 << 3,
1049         NVME_SELF_TEST_REPORTS          = 20,
1050 };
1051
1052 struct nvme_identify {
1053         __u8                    opcode;
1054         __u8                    flags;
1055         __u16                   command_id;
1056         __le32                  nsid;
1057         __u64                   rsvd2[2];
1058         union nvme_data_ptr     dptr;
1059         __u8                    cns;
1060         __u8                    rsvd3;
1061         __le16                  ctrlid;
1062         __u32                   rsvd11[5];
1063 };
1064
1065 #define NVME_IDENTIFY_DATA_SIZE 4096
1066
1067 struct nvme_features {
1068         __u8                    opcode;
1069         __u8                    flags;
1070         __u16                   command_id;
1071         __le32                  nsid;
1072         __u64                   rsvd2[2];
1073         union nvme_data_ptr     dptr;
1074         __le32                  fid;
1075         __le32                  dword11;
1076         __le32                  dword12;
1077         __le32                  dword13;
1078         __le32                  dword14;
1079         __le32                  dword15;
1080 };
1081
1082 struct nvme_host_mem_buf_desc {
1083         __le64                  addr;
1084         __le32                  size;
1085         __u32                   rsvd;
1086 };
1087
1088 struct nvme_create_cq {
1089         __u8                    opcode;
1090         __u8                    flags;
1091         __u16                   command_id;
1092         __u32                   rsvd1[5];
1093         __le64                  prp1;
1094         __u64                   rsvd8;
1095         __le16                  cqid;
1096         __le16                  qsize;
1097         __le16                  cq_flags;
1098         __le16                  irq_vector;
1099         __u32                   rsvd12[4];
1100 };
1101
1102 struct nvme_create_sq {
1103         __u8                    opcode;
1104         __u8                    flags;
1105         __u16                   command_id;
1106         __u32                   rsvd1[5];
1107         __le64                  prp1;
1108         __u64                   rsvd8;
1109         __le16                  sqid;
1110         __le16                  qsize;
1111         __le16                  sq_flags;
1112         __le16                  cqid;
1113         __u32                   rsvd12[4];
1114 };
1115
1116 struct nvme_delete_queue {
1117         __u8                    opcode;
1118         __u8                    flags;
1119         __u16                   command_id;
1120         __u32                   rsvd1[9];
1121         __le16                  qid;
1122         __u16                   rsvd10;
1123         __u32                   rsvd11[5];
1124 };
1125
1126 struct nvme_abort_cmd {
1127         __u8                    opcode;
1128         __u8                    flags;
1129         __u16                   command_id;
1130         __u32                   rsvd1[9];
1131         __le16                  sqid;
1132         __u16                   cid;
1133         __u32                   rsvd11[5];
1134 };
1135
1136 struct nvme_download_firmware {
1137         __u8                    opcode;
1138         __u8                    flags;
1139         __u16                   command_id;
1140         __u32                   rsvd1[5];
1141         union nvme_data_ptr     dptr;
1142         __le32                  numd;
1143         __le32                  offset;
1144         __u32                   rsvd12[4];
1145 };
1146
1147 struct nvme_format_cmd {
1148         __u8                    opcode;
1149         __u8                    flags;
1150         __u16                   command_id;
1151         __le32                  nsid;
1152         __u64                   rsvd2[4];
1153         __le32                  cdw10;
1154         __u32                   rsvd11[5];
1155 };
1156
1157 struct nvme_get_log_page_command {
1158         __u8                    opcode;
1159         __u8                    flags;
1160         __u16                   command_id;
1161         __le32                  nsid;
1162         __u64                   rsvd2[2];
1163         union nvme_data_ptr     dptr;
1164         __u8                    lid;
1165         __u8                    lsp;
1166         __le16                  numdl;
1167         __le16                  numdu;
1168         __u16                   rsvd11;
1169         __le32                  lpol;
1170         __le32                  lpou;
1171         __u32                   rsvd14[2];
1172 };
1173
1174 struct nvme_directive_cmd {
1175         __u8                    opcode;
1176         __u8                    flags;
1177         __u16                   command_id;
1178         __le32                  nsid;
1179         __u64                   rsvd2[2];
1180         union nvme_data_ptr     dptr;
1181         __le32                  numd;
1182         __u8                    doper;
1183         __u8                    dtype;
1184         __le16                  dspec;
1185         __u8                    endir;
1186         __u8                    tdtype;
1187         __u16                   rsvd15;
1188
1189         __u32                   rsvd16[3];
1190 };
1191
1192 /* Sanitize Log Page */
1193 struct nvme_sanitize_log_page {
1194         __le16                  progress;
1195         __le16                  status;
1196         __le32                  cdw10_info;
1197         __le32                  est_ovrwrt_time;
1198         __le32                  est_blk_erase_time;
1199         __le32                  est_crypto_erase_time;
1200         __le32                  est_ovrwrt_time_with_no_deallocate;
1201         __le32                  est_blk_erase_time_with_no_deallocate;
1202         __le32                  est_crypto_erase_time_with_no_deallocate;
1203 };
1204
1205 /*
1206  * Fabrics subcommands.
1207  */
1208 enum nvmf_fabrics_opcode {
1209         nvme_fabrics_command            = 0x7f,
1210 };
1211
1212 enum nvmf_capsule_command {
1213         nvme_fabrics_type_property_set  = 0x00,
1214         nvme_fabrics_type_connect       = 0x01,
1215         nvme_fabrics_type_property_get  = 0x04,
1216 };
1217
1218 struct nvmf_common_command {
1219         __u8    opcode;
1220         __u8    resv1;
1221         __u16   command_id;
1222         __u8    fctype;
1223         __u8    resv2[35];
1224         __u8    ts[24];
1225 };
1226
1227 /*
1228  * The legal cntlid range a NVMe Target will provide.
1229  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1230  * Devices based on earlier specs did not have the subsystem concept;
1231  * therefore, those devices had their cntlid value set to 0 as a result.
1232  */
1233 #define NVME_CNTLID_MIN         1
1234 #define NVME_CNTLID_MAX         0xffef
1235 #define NVME_CNTLID_DYNAMIC     0xffff
1236
1237 #define MAX_DISC_LOGS   255
1238
1239 /* Discovery log page entry */
1240 struct nvmf_disc_rsp_page_entry {
1241         __u8            trtype;
1242         __u8            adrfam;
1243         __u8            subtype;
1244         __u8            treq;
1245         __le16          portid;
1246         __le16          cntlid;
1247         __le16          asqsz;
1248         __u8            resv8[22];
1249         char            trsvcid[NVMF_TRSVCID_SIZE];
1250         __u8            resv64[192];
1251         char            subnqn[NVMF_NQN_FIELD_LEN];
1252         char            traddr[NVMF_TRADDR_SIZE];
1253         union tsas {
1254                 char            common[NVMF_TSAS_SIZE];
1255                 struct rdma {
1256                         __u8    qptype;
1257                         __u8    prtype;
1258                         __u8    cms;
1259                         __u8    resv3[5];
1260                         __u16   pkey;
1261                         __u8    resv10[246];
1262                 } rdma;
1263                 struct tcp {
1264                         __u8    sectype;
1265                 } tcp;
1266         } tsas;
1267 };
1268
1269 /* Discovery log page header */
1270 struct nvmf_disc_rsp_page_hdr {
1271         __le64          genctr;
1272         __le64          numrec;
1273         __le16          recfmt;
1274         __u8            resv14[1006];
1275         struct nvmf_disc_rsp_page_entry entries[0];
1276 };
1277
1278 struct nvmf_connect_command {
1279         __u8            opcode;
1280         __u8            resv1;
1281         __u16           command_id;
1282         __u8            fctype;
1283         __u8            resv2[19];
1284         union nvme_data_ptr dptr;
1285         __le16          recfmt;
1286         __le16          qid;
1287         __le16          sqsize;
1288         __u8            cattr;
1289         __u8            resv3;
1290         __le32          kato;
1291         __u8            resv4[12];
1292 };
1293
1294 struct nvmf_connect_data {
1295         uuid_t          hostid;
1296         __le16          cntlid;
1297         char            resv4[238];
1298         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1299         char            hostnqn[NVMF_NQN_FIELD_LEN];
1300         char            resv5[256];
1301 };
1302
1303 struct nvmf_property_set_command {
1304         __u8            opcode;
1305         __u8            resv1;
1306         __u16           command_id;
1307         __u8            fctype;
1308         __u8            resv2[35];
1309         __u8            attrib;
1310         __u8            resv3[3];
1311         __le32          offset;
1312         __le64          value;
1313         __u8            resv4[8];
1314 };
1315
1316 struct nvmf_property_get_command {
1317         __u8            opcode;
1318         __u8            resv1;
1319         __u16           command_id;
1320         __u8            fctype;
1321         __u8            resv2[35];
1322         __u8            attrib;
1323         __u8            resv3[3];
1324         __le32          offset;
1325         __u8            resv4[16];
1326 };
1327
1328 struct nvme_dbbuf {
1329         __u8                    opcode;
1330         __u8                    flags;
1331         __u16                   command_id;
1332         __u32                   rsvd1[5];
1333         __le64                  prp1;
1334         __le64                  prp2;
1335         __u32                   rsvd12[6];
1336 };
1337
1338 struct streams_directive_params {
1339         __le16  msl;
1340         __le16  nssa;
1341         __le16  nsso;
1342         __u8    rsvd[10];
1343         __le32  sws;
1344         __le16  sgs;
1345         __le16  nsa;
1346         __le16  nso;
1347         __u8    rsvd2[6];
1348 };
1349
1350 struct nvme_command {
1351         union {
1352                 struct nvme_common_command common;
1353                 struct nvme_rw_command rw;
1354                 struct nvme_identify identify;
1355                 struct nvme_features features;
1356                 struct nvme_create_cq create_cq;
1357                 struct nvme_create_sq create_sq;
1358                 struct nvme_delete_queue delete_queue;
1359                 struct nvme_download_firmware dlfw;
1360                 struct nvme_format_cmd format;
1361                 struct nvme_dsm_cmd dsm;
1362                 struct nvme_write_zeroes_cmd write_zeroes;
1363                 struct nvme_abort_cmd abort;
1364                 struct nvme_get_log_page_command get_log_page;
1365                 struct nvmf_common_command fabrics;
1366                 struct nvmf_connect_command connect;
1367                 struct nvmf_property_set_command prop_set;
1368                 struct nvmf_property_get_command prop_get;
1369                 struct nvme_dbbuf dbbuf;
1370                 struct nvme_directive_cmd directive;
1371         };
1372 };
1373
1374 static inline bool nvme_is_write(struct nvme_command *cmd)
1375 {
1376         /*
1377          * What a mess...
1378          *
1379          * Why can't we simply have a Fabrics In and Fabrics out command?
1380          */
1381         if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1382                 return cmd->fabrics.fctype & 1;
1383         return cmd->common.opcode & 1;
1384 }
1385
1386 enum {
1387         NVME_SCT_GENERIC                = 0x0,
1388         NVME_SCT_CMD_SPECIFIC           = 0x1,
1389         NVME_SCT_MEDIA                  = 0x2,
1390 };
1391
1392 enum {
1393         /*
1394          * Generic Command Status:
1395          */
1396         NVME_SC_SUCCESS                 = 0x0,
1397         NVME_SC_INVALID_OPCODE          = 0x1,
1398         NVME_SC_INVALID_FIELD           = 0x2,
1399         NVME_SC_CMDID_CONFLICT          = 0x3,
1400         NVME_SC_DATA_XFER_ERROR         = 0x4,
1401         NVME_SC_POWER_LOSS              = 0x5,
1402         NVME_SC_INTERNAL                = 0x6,
1403         NVME_SC_ABORT_REQ               = 0x7,
1404         NVME_SC_ABORT_QUEUE             = 0x8,
1405         NVME_SC_FUSED_FAIL              = 0x9,
1406         NVME_SC_FUSED_MISSING           = 0xa,
1407         NVME_SC_INVALID_NS              = 0xb,
1408         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1409         NVME_SC_SGL_INVALID_LAST        = 0xd,
1410         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1411         NVME_SC_SGL_INVALID_DATA        = 0xf,
1412         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1413         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1414
1415         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1416         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1417
1418         NVME_SC_SANITIZE_FAILED         = 0x1C,
1419         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1420
1421         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1422         NVME_SC_CMD_INTERRUPTED         = 0x21,
1423
1424         NVME_SC_LBA_RANGE               = 0x80,
1425         NVME_SC_CAP_EXCEEDED            = 0x81,
1426         NVME_SC_NS_NOT_READY            = 0x82,
1427         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1428
1429         /*
1430          * Command Specific Status:
1431          */
1432         NVME_SC_CQ_INVALID              = 0x100,
1433         NVME_SC_QID_INVALID             = 0x101,
1434         NVME_SC_QUEUE_SIZE              = 0x102,
1435         NVME_SC_ABORT_LIMIT             = 0x103,
1436         NVME_SC_ABORT_MISSING           = 0x104,
1437         NVME_SC_ASYNC_LIMIT             = 0x105,
1438         NVME_SC_FIRMWARE_SLOT           = 0x106,
1439         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1440         NVME_SC_INVALID_VECTOR          = 0x108,
1441         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1442         NVME_SC_INVALID_FORMAT          = 0x10a,
1443         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1444         NVME_SC_INVALID_QUEUE           = 0x10c,
1445         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1446         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1447         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1448         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1449         NVME_SC_FW_NEEDS_RESET          = 0x111,
1450         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1451         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1452         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1453         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1454         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1455         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1456         NVME_SC_NS_IS_PRIVATE           = 0x119,
1457         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1458         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1459         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1460         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1461         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1462
1463         /*
1464          * I/O Command Set Specific - NVM commands:
1465          */
1466         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1467         NVME_SC_INVALID_PI              = 0x181,
1468         NVME_SC_READ_ONLY               = 0x182,
1469         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1470
1471         /*
1472          * I/O Command Set Specific - Fabrics commands:
1473          */
1474         NVME_SC_CONNECT_FORMAT          = 0x180,
1475         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1476         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1477         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1478         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1479
1480         NVME_SC_DISCOVERY_RESTART       = 0x190,
1481         NVME_SC_AUTH_REQUIRED           = 0x191,
1482
1483         /*
1484          * Media and Data Integrity Errors:
1485          */
1486         NVME_SC_WRITE_FAULT             = 0x280,
1487         NVME_SC_READ_ERROR              = 0x281,
1488         NVME_SC_GUARD_CHECK             = 0x282,
1489         NVME_SC_APPTAG_CHECK            = 0x283,
1490         NVME_SC_REFTAG_CHECK            = 0x284,
1491         NVME_SC_COMPARE_FAILED          = 0x285,
1492         NVME_SC_ACCESS_DENIED           = 0x286,
1493         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1494
1495         /*
1496          * Path-related Errors:
1497          */
1498         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1499         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1500         NVME_SC_ANA_TRANSITION          = 0x303,
1501
1502         NVME_SC_CRD                     = 0x1800,
1503         NVME_SC_DNR                     = 0x4000,
1504 };
1505
1506 struct nvme_completion {
1507         /*
1508          * Used by Admin and Fabrics commands to return data:
1509          */
1510         union nvme_result {
1511                 __le16  u16;
1512                 __le32  u32;
1513                 __le64  u64;
1514         } result;
1515         __le16  sq_head;        /* how much of this queue may be reclaimed */
1516         __le16  sq_id;          /* submission queue that generated this entry */
1517         __u16   command_id;     /* of the command which completed */
1518         __le16  status;         /* did the command fail, and if so, why? */
1519 };
1520
1521 #define NVME_VS(major, minor, tertiary) \
1522         (((major) << 16) | ((minor) << 8) | (tertiary))
1523
1524 #define NVME_MAJOR(ver)         ((ver) >> 16)
1525 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1526 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1527
1528 #endif /* _LINUX_NVME_H */