68000eb8c1dc42fd6d886ed748c1f651862aa6de
[multipath-tools/.git] / libmultipath / nvme / linux / nvme.h
1 /*
2  * Definitions for the NVM Express interface
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <linux/types.h>
19 #include <linux/uuid.h>
20
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN      256
23
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE           223
26
27 #define NVMF_TRSVCID_SIZE       32
28 #define NVMF_TRADDR_SIZE        256
29 #define NVMF_TSAS_SIZE          256
30
31 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
32
33 #define NVME_RDMA_IP_PORT       4420
34
35 #define NVME_NSID_ALL           0xffffffff
36
37 enum nvme_subsys_type {
38         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
39         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
40 };
41
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
43 enum {
44         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
45         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
46         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
47         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
48         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
49 };
50
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
52 enum {
53         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
54         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
55         NVMF_TRTYPE_TCP         = 3,    /* TCP */
56         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
57         NVMF_TRTYPE_MAX,
58 };
59
60 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
61 enum {
62         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
63         NVMF_TREQ_REQUIRED      = 1,            /* Required */
64         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
65         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* SQ flow control disable supported */
66 };
67
68 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
69  * RDMA_QPTYPE field
70  */
71 enum {
72         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
73         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
74 };
75
76 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
77  * RDMA_QPTYPE field
78  */
79 enum {
80         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
81         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
82         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
83         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
84         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
85 };
86
87 /* RDMA Connection Management Service Type codes for Discovery Log Page
88  * entry TSAS RDMA_CMS field
89  */
90 enum {
91         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
92 };
93
94 /* TCP port security type for  Discovery Log Page entry TSAS
95  */
96 enum {
97         NVMF_TCP_SECTYPE_NONE   = 0, /* No Security */
98         NVMF_TCP_SECTYPE_TLS    = 1, /* Transport Layer Security */
99 };
100
101 #define NVME_AQ_DEPTH           32
102 #define NVME_NR_AEN_COMMANDS    1
103 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
104
105 /*
106  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
107  * NVM-Express 1.2 specification, section 4.1.2.
108  */
109 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
110
111 enum {
112         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
113         NVME_REG_VS     = 0x0008,       /* Version */
114         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
115         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
116         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
117         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
118         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
119         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
120         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
121         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
122         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
123         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
124         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
125         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
126         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer Location */
127         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
128 };
129
130 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
131 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
132 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
133 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
134 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
135 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
136
137 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
138 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
139 #define NVME_CMB_SZ(cmbsz)      (((cmbsz) >> 12) & 0xfffff)
140 #define NVME_CMB_SZU(cmbsz)     (((cmbsz) >> 8) & 0xf)
141
142 #define NVME_CMB_WDS(cmbsz)     ((cmbsz) & 0x10)
143 #define NVME_CMB_RDS(cmbsz)     ((cmbsz) & 0x8)
144 #define NVME_CMB_LISTS(cmbsz)   ((cmbsz) & 0x4)
145 #define NVME_CMB_CQS(cmbsz)     ((cmbsz) & 0x2)
146 #define NVME_CMB_SQS(cmbsz)     ((cmbsz) & 0x1)
147
148 /*
149  * Submission and Completion Queue Entry Sizes for the NVM command set.
150  * (In bytes and specified as a power of two (2^n)).
151  */
152 #define NVME_NVM_IOSQES         6
153 #define NVME_NVM_IOCQES         4
154
155 enum {
156         NVME_CC_ENABLE          = 1 << 0,
157         NVME_CC_CSS_NVM         = 0 << 4,
158         NVME_CC_EN_SHIFT        = 0,
159         NVME_CC_CSS_SHIFT       = 4,
160         NVME_CC_MPS_SHIFT       = 7,
161         NVME_CC_AMS_SHIFT       = 11,
162         NVME_CC_SHN_SHIFT       = 14,
163         NVME_CC_IOSQES_SHIFT    = 16,
164         NVME_CC_IOCQES_SHIFT    = 20,
165         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
166         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
167         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
168         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
169         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
170         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
171         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
172         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
173         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
174         NVME_CSTS_RDY           = 1 << 0,
175         NVME_CSTS_CFS           = 1 << 1,
176         NVME_CSTS_NSSRO         = 1 << 4,
177         NVME_CSTS_PP            = 1 << 5,
178         NVME_CSTS_SHST_NORMAL   = 0 << 2,
179         NVME_CSTS_SHST_OCCUR    = 1 << 2,
180         NVME_CSTS_SHST_CMPLT    = 2 << 2,
181         NVME_CSTS_SHST_MASK     = 3 << 2,
182 };
183
184 struct nvme_id_power_state {
185         __le16                  max_power;      /* centiwatts */
186         __u8                    rsvd2;
187         __u8                    flags;
188         __le32                  entry_lat;      /* microseconds */
189         __le32                  exit_lat;       /* microseconds */
190         __u8                    read_tput;
191         __u8                    read_lat;
192         __u8                    write_tput;
193         __u8                    write_lat;
194         __le16                  idle_power;
195         __u8                    idle_scale;
196         __u8                    rsvd19;
197         __le16                  active_power;
198         __u8                    active_work_scale;
199         __u8                    rsvd23[9];
200 };
201
202 enum {
203         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
204         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
205 };
206
207 struct nvme_id_ctrl {
208         __le16                  vid;
209         __le16                  ssvid;
210         char                    sn[20];
211         char                    mn[40];
212         char                    fr[8];
213         __u8                    rab;
214         __u8                    ieee[3];
215         __u8                    cmic;
216         __u8                    mdts;
217         __le16                  cntlid;
218         __le32                  ver;
219         __le32                  rtd3r;
220         __le32                  rtd3e;
221         __le32                  oaes;
222         __le32                  ctratt;
223         __le16                  rrls;
224         __u8                    rsvd102[154];
225         __le16                  oacs;
226         __u8                    acl;
227         __u8                    aerl;
228         __u8                    frmw;
229         __u8                    lpa;
230         __u8                    elpe;
231         __u8                    npss;
232         __u8                    avscc;
233         __u8                    apsta;
234         __le16                  wctemp;
235         __le16                  cctemp;
236         __le16                  mtfa;
237         __le32                  hmpre;
238         __le32                  hmmin;
239         __u8                    tnvmcap[16];
240         __u8                    unvmcap[16];
241         __le32                  rpmbs;
242         __le16                  edstt;
243         __u8                    dsto;
244         __u8                    fwug;
245         __le16                  kas;
246         __le16                  hctma;
247         __le16                  mntmt;
248         __le16                  mxtmt;
249         __le32                  sanicap;
250         __le32                  hmminds;
251         __le16                  hmmaxd;
252         __le16                  nsetidmax;
253         __u8                    rsvd340[2];
254         __u8                    anatt;
255         __u8                    anacap;
256         __le32                  anagrpmax;
257         __le32                  nanagrpid;
258         __u8                    rsvd352[160];
259         __u8                    sqes;
260         __u8                    cqes;
261         __le16                  maxcmd;
262         __le32                  nn;
263         __le16                  oncs;
264         __le16                  fuses;
265         __u8                    fna;
266         __u8                    vwc;
267         __le16                  awun;
268         __le16                  awupf;
269         __u8                    nvscc;
270         __u8                    nwpc;
271         __le16                  acwu;
272         __u8                    rsvd534[2];
273         __le32                  sgls;
274         __le32                  mnan;
275         __u8                    rsvd544[224];
276         char                    subnqn[256];
277         __u8                    rsvd1024[768];
278         __le32                  ioccsz;
279         __le32                  iorcsz;
280         __le16                  icdoff;
281         __u8                    ctrattr;
282         __u8                    msdbd;
283         __u8                    rsvd1804[244];
284         struct nvme_id_power_state      psd[32];
285         __u8                    vs[1024];
286 };
287
288 enum {
289         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
290         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
291         NVME_CTRL_ONCS_DSM                      = 1 << 2,
292         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
293         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
294         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
295         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
296         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
297         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
298         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
299         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
300         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
301         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
302         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
303         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
304         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
305 };
306
307 struct nvme_lbaf {
308         __le16                  ms;
309         __u8                    ds;
310         __u8                    rp;
311 };
312
313 struct nvme_id_ns {
314         __le64                  nsze;
315         __le64                  ncap;
316         __le64                  nuse;
317         __u8                    nsfeat;
318         __u8                    nlbaf;
319         __u8                    flbas;
320         __u8                    mc;
321         __u8                    dpc;
322         __u8                    dps;
323         __u8                    nmic;
324         __u8                    rescap;
325         __u8                    fpi;
326         __u8                    dlfeat;
327         __le16                  nawun;
328         __le16                  nawupf;
329         __le16                  nacwu;
330         __le16                  nabsn;
331         __le16                  nabo;
332         __le16                  nabspf;
333         __le16                  noiob;
334         __u8                    nvmcap[16];
335         __u8                    rsvd64[28];
336         __le32                  anagrpid;
337         __u8                    rsvd96[3];
338         __u8                    nsattr;
339         __le16                  nvmsetid;
340         __le16                  endgid;
341         __u8                    nguid[16];
342         __u8                    eui64[8];
343         struct nvme_lbaf        lbaf[16];
344         __u8                    rsvd192[192];
345         __u8                    vs[3712];
346 };
347
348 enum {
349         NVME_ID_CNS_NS                  = 0x00,
350         NVME_ID_CNS_CTRL                = 0x01,
351         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
352         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
353         NVME_ID_CNS_NVMSET_LIST         = 0x04,
354         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
355         NVME_ID_CNS_NS_PRESENT          = 0x11,
356         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
357         NVME_ID_CNS_CTRL_LIST           = 0x13,
358 };
359
360 enum {
361         NVME_DIR_IDENTIFY               = 0x00,
362         NVME_DIR_STREAMS                = 0x01,
363         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
364         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
365         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
366         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
367         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
368         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
369         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
370         NVME_DIR_ENDIR                  = 0x01,
371 };
372
373 enum {
374         NVME_NS_FEAT_THIN       = 1 << 0,
375         NVME_NS_FLBAS_LBA_MASK  = 0xf,
376         NVME_NS_FLBAS_META_EXT  = 0x10,
377         NVME_LBAF_RP_BEST       = 0,
378         NVME_LBAF_RP_BETTER     = 1,
379         NVME_LBAF_RP_GOOD       = 2,
380         NVME_LBAF_RP_DEGRADED   = 3,
381         NVME_NS_DPC_PI_LAST     = 1 << 4,
382         NVME_NS_DPC_PI_FIRST    = 1 << 3,
383         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
384         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
385         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
386         NVME_NS_DPS_PI_FIRST    = 1 << 3,
387         NVME_NS_DPS_PI_MASK     = 0x7,
388         NVME_NS_DPS_PI_TYPE1    = 1,
389         NVME_NS_DPS_PI_TYPE2    = 2,
390         NVME_NS_DPS_PI_TYPE3    = 3,
391 };
392
393 struct nvme_ns_id_desc {
394         __u8 nidt;
395         __u8 nidl;
396         __le16 reserved;
397 };
398
399 #define NVME_NIDT_EUI64_LEN     8
400 #define NVME_NIDT_NGUID_LEN     16
401 #define NVME_NIDT_UUID_LEN      16
402
403 enum {
404         NVME_NIDT_EUI64         = 0x01,
405         NVME_NIDT_NGUID         = 0x02,
406         NVME_NIDT_UUID          = 0x03,
407 };
408
409 #define NVME_MAX_NVMSET         31
410
411 struct nvme_nvmset_attr_entry {
412         __le16                  id;
413         __le16                  endurance_group_id;
414         __u8                    rsvd4[4];
415         __le32                  random_4k_read_typical;
416         __le32                  opt_write_size;
417         __u8                    total_nvmset_cap[16];
418         __u8                    unalloc_nvmset_cap[16];
419         __u8                    rsvd48[80];
420 };
421
422 struct nvme_id_nvmset {
423         __u8                            nid;
424         __u8                            rsvd1[127];
425         struct nvme_nvmset_attr_entry   ent[NVME_MAX_NVMSET];
426 };
427
428 /* Derived from 1.3a Figure 101: Get Log Page – Telemetry Host
429  * -Initiated Log (Log Identifier 07h)
430  */
431 struct nvme_telemetry_log_page_hdr {
432         __u8    lpi; /* Log page identifier */
433         __u8    rsvd[4];
434         __u8    iee_oui[3];
435         __u16   dalb1; /* Data area 1 last block */
436         __u16   dalb2; /* Data area 2 last block */
437         __u16   dalb3; /* Data area 3 last block */
438         __u8    rsvd1[368]; /* TODO verify */
439         __u8    ctrlavail; /* Controller initiated data avail?*/
440         __u8    ctrldgn; /* Controller initiated telemetry Data Gen # */
441         __u8    rsnident[128];
442         /* We'll have to double fetch so we can get the header,
443          * parse dalb1->3 determine how much size we need for the
444          * log then alloc below. Or just do a secondary non-struct
445          * allocation.
446          */
447         __u8    telemetry_dataarea[0];
448 };
449
450 struct nvme_endurance_group_log {
451         __u32   rsvd0;
452         __u8    avl_spare_threshold;
453         __u8    percent_used;
454         __u8    rsvd6[26];
455         __u8    endurance_estimate[16];
456         __u8    data_units_read[16];
457         __u8    data_units_written[16];
458         __u8    media_units_written[16];
459         __u8    rsvd96[416];
460 };
461
462 struct nvme_smart_log {
463         __u8                    critical_warning;
464         __u8                    temperature[2];
465         __u8                    avail_spare;
466         __u8                    spare_thresh;
467         __u8                    percent_used;
468         __u8                    rsvd6[26];
469         __u8                    data_units_read[16];
470         __u8                    data_units_written[16];
471         __u8                    host_reads[16];
472         __u8                    host_writes[16];
473         __u8                    ctrl_busy_time[16];
474         __u8                    power_cycles[16];
475         __u8                    power_on_hours[16];
476         __u8                    unsafe_shutdowns[16];
477         __u8                    media_errors[16];
478         __u8                    num_err_log_entries[16];
479         __le32                  warning_temp_time;
480         __le32                  critical_comp_time;
481         __le16                  temp_sensor[8];
482         __le32                  thm_temp1_trans_count;
483         __le32                  thm_temp2_trans_count;
484         __le32                  thm_temp1_total_time;
485         __le32                  thm_temp2_total_time;
486         __u8                    rsvd232[280];
487 };
488
489 struct nvme_self_test_res {
490         __u8                    device_self_test_status;
491         __u8                    segment_num;
492         __u8                    valid_diagnostic_info;
493         __u8                    rsvd;
494         __le64                  power_on_hours;
495         __le32                  nsid;
496         __le64                  failing_lba;
497         __u8                    status_code_type;
498         __u8                    status_code;
499         __u8                    vendor_specific[2];
500 } __attribute__((packed));
501
502 struct nvme_self_test_log {
503         __u8                      crnt_dev_selftest_oprn;
504         __u8                      crnt_dev_selftest_compln;
505         __u8                      rsvd[2];
506         struct nvme_self_test_res result[20];
507 } __attribute__((packed));
508
509 struct nvme_fw_slot_info_log {
510         __u8                    afi;
511         __u8                    rsvd1[7];
512         __le64                  frs[7];
513         __u8                    rsvd64[448];
514 };
515
516 /* NVMe Namespace Write Protect State */
517 enum {
518         NVME_NS_NO_WRITE_PROTECT = 0,
519         NVME_NS_WRITE_PROTECT,
520         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
521         NVME_NS_WRITE_PROTECT_PERMANENT,
522 };
523
524 #define NVME_MAX_CHANGED_NAMESPACES     1024
525
526 struct nvme_changed_ns_list_log {
527         __le32                  log[NVME_MAX_CHANGED_NAMESPACES];
528 };
529
530 enum {
531         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
532         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
533         NVME_CMD_EFFECTS_NCC            = 1 << 2,
534         NVME_CMD_EFFECTS_NIC            = 1 << 3,
535         NVME_CMD_EFFECTS_CCC            = 1 << 4,
536         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
537 };
538
539 struct nvme_effects_log {
540         __le32 acs[256];
541         __le32 iocs[256];
542         __u8   resv[2048];
543 };
544
545 enum nvme_ana_state {
546         NVME_ANA_OPTIMIZED              = 0x01,
547         NVME_ANA_NONOPTIMIZED           = 0x02,
548         NVME_ANA_INACCESSIBLE           = 0x03,
549         NVME_ANA_PERSISTENT_LOSS        = 0x04,
550         NVME_ANA_CHANGE                 = 0x0f,
551 };
552
553 struct nvme_ana_group_desc {
554         __le32  grpid;
555         __le32  nnsids;
556         __le64  chgcnt;
557         __u8    state;
558         __u8    rsvd17[15];
559         __le32  nsids[];
560 };
561
562 /* flag for the log specific field of the ANA log */
563 #define NVME_ANA_LOG_RGO   (1 << 0)
564
565 struct nvme_ana_rsp_hdr {
566         __le64  chgcnt;
567         __le16  ngrps;
568         __le16  rsvd10[3];
569 };
570
571 enum {
572         NVME_SMART_CRIT_SPARE           = 1 << 0,
573         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
574         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
575         NVME_SMART_CRIT_MEDIA           = 1 << 3,
576         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
577 };
578
579 enum {
580         NVME_AER_ERROR                  = 0,
581         NVME_AER_SMART                  = 1,
582         NVME_AER_CSS                    = 6,
583         NVME_AER_VS                     = 7,
584         NVME_AER_NOTICE_NS_CHANGED      = 0x0002,
585         NVME_AER_NOTICE_ANA             = 0x0003,
586         NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
587 };
588
589 struct nvme_lba_range_type {
590         __u8                    type;
591         __u8                    attributes;
592         __u8                    rsvd2[14];
593         __u64                   slba;
594         __u64                   nlb;
595         __u8                    guid[16];
596         __u8                    rsvd48[16];
597 };
598
599 enum {
600         NVME_LBART_TYPE_FS      = 0x01,
601         NVME_LBART_TYPE_RAID    = 0x02,
602         NVME_LBART_TYPE_CACHE   = 0x03,
603         NVME_LBART_TYPE_SWAP    = 0x04,
604
605         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
606         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
607 };
608
609 struct nvme_plm_config {
610         __u16   enable_event;
611         __u8    rsvd2[30];
612         __u64   dtwin_reads_thresh;
613         __u64   dtwin_writes_thresh;
614         __u64   dtwin_time_thresh;
615         __u8    rsvd56[456];
616 };
617
618 struct nvme_reservation_status {
619         __le32  gen;
620         __u8    rtype;
621         __u8    regctl[2];
622         __u8    resv5[2];
623         __u8    ptpls;
624         __u8    resv10[13];
625         struct {
626                 __le16  cntlid;
627                 __u8    rcsts;
628                 __u8    resv3[5];
629                 __le64  hostid;
630                 __le64  rkey;
631         } regctl_ds[];
632 };
633
634 struct nvme_reservation_status_ext {
635         __le32  gen;
636         __u8    rtype;
637         __u8    regctl[2];
638         __u8    resv5[2];
639         __u8    ptpls;
640         __u8    resv10[14];
641         __u8    resv24[40];
642         struct {
643                 __le16  cntlid;
644                 __u8    rcsts;
645                 __u8    resv3[5];
646                 __le64  rkey;
647                 __u8    hostid[16];
648                 __u8    resv32[32];
649         } regctl_eds[];
650 };
651
652 enum nvme_async_event_type {
653         NVME_AER_TYPE_ERROR     = 0,
654         NVME_AER_TYPE_SMART     = 1,
655         NVME_AER_TYPE_NOTICE    = 2,
656 };
657
658 /* I/O commands */
659
660 enum nvme_opcode {
661         nvme_cmd_flush          = 0x00,
662         nvme_cmd_write          = 0x01,
663         nvme_cmd_read           = 0x02,
664         nvme_cmd_write_uncor    = 0x04,
665         nvme_cmd_compare        = 0x05,
666         nvme_cmd_write_zeroes   = 0x08,
667         nvme_cmd_dsm            = 0x09,
668         nvme_cmd_resv_register  = 0x0d,
669         nvme_cmd_resv_report    = 0x0e,
670         nvme_cmd_resv_acquire   = 0x11,
671         nvme_cmd_resv_release   = 0x15,
672 };
673
674 /*
675  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
676  *
677  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
678  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
679  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
680  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
681  *                            request subtype
682  */
683 enum {
684         NVME_SGL_FMT_ADDRESS            = 0x00,
685         NVME_SGL_FMT_OFFSET             = 0x01,
686         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
687         NVME_SGL_FMT_INVALIDATE         = 0x0f,
688 };
689
690 /*
691  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
692  *
693  * For struct nvme_sgl_desc:
694  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
695  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
696  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
697  *
698  * For struct nvme_keyed_sgl_desc:
699  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
700  *
701  * Transport-specific SGL types:
702  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
703  */
704 enum {
705         NVME_SGL_FMT_DATA_DESC          = 0x00,
706         NVME_SGL_FMT_SEG_DESC           = 0x02,
707         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
708         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
709         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
710 };
711
712 struct nvme_sgl_desc {
713         __le64  addr;
714         __le32  length;
715         __u8    rsvd[3];
716         __u8    type;
717 };
718
719 struct nvme_keyed_sgl_desc {
720         __le64  addr;
721         __u8    length[3];
722         __u8    key[4];
723         __u8    type;
724 };
725
726 union nvme_data_ptr {
727         struct {
728                 __le64  prp1;
729                 __le64  prp2;
730         };
731         struct nvme_sgl_desc    sgl;
732         struct nvme_keyed_sgl_desc ksgl;
733 };
734
735 /*
736  * Lowest two bits of our flags field (FUSE field in the spec):
737  *
738  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
739  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
740  *
741  * Highest two bits in our flags field (PSDT field in the spec):
742  *
743  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
744  *      If used, MPTR contains addr of single physical buffer (byte aligned).
745  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
746  *      If used, MPTR contains an address of an SGL segment containing
747  *      exactly 1 SGL descriptor (qword aligned).
748  */
749 enum {
750         NVME_CMD_FUSE_FIRST     = (1 << 0),
751         NVME_CMD_FUSE_SECOND    = (1 << 1),
752
753         NVME_CMD_SGL_METABUF    = (1 << 6),
754         NVME_CMD_SGL_METASEG    = (1 << 7),
755         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
756 };
757
758 struct nvme_common_command {
759         __u8                    opcode;
760         __u8                    flags;
761         __u16                   command_id;
762         __le32                  nsid;
763         __le32                  cdw2[2];
764         __le64                  metadata;
765         union nvme_data_ptr     dptr;
766         __le32                  cdw10[6];
767 };
768
769 struct nvme_rw_command {
770         __u8                    opcode;
771         __u8                    flags;
772         __u16                   command_id;
773         __le32                  nsid;
774         __u64                   rsvd2;
775         __le64                  metadata;
776         union nvme_data_ptr     dptr;
777         __le64                  slba;
778         __le16                  length;
779         __le16                  control;
780         __le32                  dsmgmt;
781         __le32                  reftag;
782         __le16                  apptag;
783         __le16                  appmask;
784 };
785
786 enum {
787         NVME_RW_LR                      = 1 << 15,
788         NVME_RW_FUA                     = 1 << 14,
789         NVME_RW_DEAC                    = 1 << 9,
790         NVME_RW_DSM_FREQ_UNSPEC         = 0,
791         NVME_RW_DSM_FREQ_TYPICAL        = 1,
792         NVME_RW_DSM_FREQ_RARE           = 2,
793         NVME_RW_DSM_FREQ_READS          = 3,
794         NVME_RW_DSM_FREQ_WRITES         = 4,
795         NVME_RW_DSM_FREQ_RW             = 5,
796         NVME_RW_DSM_FREQ_ONCE           = 6,
797         NVME_RW_DSM_FREQ_PREFETCH       = 7,
798         NVME_RW_DSM_FREQ_TEMP           = 8,
799         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
800         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
801         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
802         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
803         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
804         NVME_RW_DSM_COMPRESSED          = 1 << 7,
805         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
806         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
807         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
808         NVME_RW_PRINFO_PRACT            = 1 << 13,
809         NVME_RW_DTYPE_STREAMS           = 1 << 4,
810 };
811
812 struct nvme_dsm_cmd {
813         __u8                    opcode;
814         __u8                    flags;
815         __u16                   command_id;
816         __le32                  nsid;
817         __u64                   rsvd2[2];
818         union nvme_data_ptr     dptr;
819         __le32                  nr;
820         __le32                  attributes;
821         __u32                   rsvd12[4];
822 };
823
824 enum {
825         NVME_DSMGMT_IDR         = 1 << 0,
826         NVME_DSMGMT_IDW         = 1 << 1,
827         NVME_DSMGMT_AD          = 1 << 2,
828 };
829
830 #define NVME_DSM_MAX_RANGES     256
831
832 struct nvme_dsm_range {
833         __le32                  cattr;
834         __le32                  nlb;
835         __le64                  slba;
836 };
837
838 struct nvme_write_zeroes_cmd {
839         __u8                    opcode;
840         __u8                    flags;
841         __u16                   command_id;
842         __le32                  nsid;
843         __u64                   rsvd2;
844         __le64                  metadata;
845         union nvme_data_ptr     dptr;
846         __le64                  slba;
847         __le16                  length;
848         __le16                  control;
849         __le32                  dsmgmt;
850         __le32                  reftag;
851         __le16                  apptag;
852         __le16                  appmask;
853 };
854
855 /* Features */
856
857 struct nvme_feat_auto_pst {
858         __le64 entries[32];
859 };
860
861 enum {
862         NVME_HOST_MEM_ENABLE    = (1 << 0),
863         NVME_HOST_MEM_RETURN    = (1 << 1),
864 };
865
866 /* Admin commands */
867
868 enum nvme_admin_opcode {
869         nvme_admin_delete_sq            = 0x00,
870         nvme_admin_create_sq            = 0x01,
871         nvme_admin_get_log_page         = 0x02,
872         nvme_admin_delete_cq            = 0x04,
873         nvme_admin_create_cq            = 0x05,
874         nvme_admin_identify             = 0x06,
875         nvme_admin_abort_cmd            = 0x08,
876         nvme_admin_set_features         = 0x09,
877         nvme_admin_get_features         = 0x0a,
878         nvme_admin_async_event          = 0x0c,
879         nvme_admin_ns_mgmt              = 0x0d,
880         nvme_admin_activate_fw          = 0x10,
881         nvme_admin_download_fw          = 0x11,
882         nvme_admin_dev_self_test        = 0x14,
883         nvme_admin_ns_attach            = 0x15,
884         nvme_admin_keep_alive           = 0x18,
885         nvme_admin_directive_send       = 0x19,
886         nvme_admin_directive_recv       = 0x1a,
887         nvme_admin_virtual_mgmt         = 0x1c,
888         nvme_admin_nvme_mi_send         = 0x1d,
889         nvme_admin_nvme_mi_recv         = 0x1e,
890         nvme_admin_dbbuf                = 0x7C,
891         nvme_admin_format_nvm           = 0x80,
892         nvme_admin_security_send        = 0x81,
893         nvme_admin_security_recv        = 0x82,
894         nvme_admin_sanitize_nvm         = 0x84,
895 };
896
897 enum {
898         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
899         NVME_CQ_IRQ_ENABLED     = (1 << 1),
900         NVME_SQ_PRIO_URGENT     = (0 << 1),
901         NVME_SQ_PRIO_HIGH       = (1 << 1),
902         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
903         NVME_SQ_PRIO_LOW        = (3 << 1),
904         NVME_FEAT_ARBITRATION   = 0x01,
905         NVME_FEAT_POWER_MGMT    = 0x02,
906         NVME_FEAT_LBA_RANGE     = 0x03,
907         NVME_FEAT_TEMP_THRESH   = 0x04,
908         NVME_FEAT_ERR_RECOVERY  = 0x05,
909         NVME_FEAT_VOLATILE_WC   = 0x06,
910         NVME_FEAT_NUM_QUEUES    = 0x07,
911         NVME_FEAT_IRQ_COALESCE  = 0x08,
912         NVME_FEAT_IRQ_CONFIG    = 0x09,
913         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
914         NVME_FEAT_ASYNC_EVENT   = 0x0b,
915         NVME_FEAT_AUTO_PST      = 0x0c,
916         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
917         NVME_FEAT_TIMESTAMP     = 0x0e,
918         NVME_FEAT_KATO          = 0x0f,
919         NVME_FEAT_HCTM          = 0X10,
920         NVME_FEAT_NOPSC         = 0X11,
921         NVME_FEAT_RRL           = 0x12,
922         NVME_FEAT_PLM_CONFIG    = 0x13,
923         NVME_FEAT_PLM_WINDOW    = 0x14,
924         NVME_FEAT_SW_PROGRESS   = 0x80,
925         NVME_FEAT_HOST_ID       = 0x81,
926         NVME_FEAT_RESV_MASK     = 0x82,
927         NVME_FEAT_RESV_PERSIST  = 0x83,
928         NVME_FEAT_WRITE_PROTECT = 0x84,
929         NVME_LOG_ERROR          = 0x01,
930         NVME_LOG_SMART          = 0x02,
931         NVME_LOG_FW_SLOT        = 0x03,
932         NVME_LOG_CHANGED_NS     = 0x04,
933         NVME_LOG_CMD_EFFECTS    = 0x05,
934         NVME_LOG_DEVICE_SELF_TEST = 0x06,
935         NVME_LOG_TELEMETRY_HOST = 0x07,
936         NVME_LOG_TELEMETRY_CTRL = 0x08,
937         NVME_LOG_ENDURANCE_GROUP = 0x09,
938         NVME_LOG_ANA            = 0x0c,
939         NVME_LOG_DISC           = 0x70,
940         NVME_LOG_RESERVATION    = 0x80,
941         NVME_LOG_SANITIZE       = 0x81,
942         NVME_FWACT_REPL         = (0 << 3),
943         NVME_FWACT_REPL_ACTV    = (1 << 3),
944         NVME_FWACT_ACTV         = (2 << 3),
945 };
946
947 enum {
948         NVME_NO_LOG_LSP       = 0x0,
949         NVME_NO_LOG_LPO       = 0x0,
950         NVME_LOG_ANA_LSP_RGO  = 0x1,
951         NVME_TELEM_LSP_CREATE = 0x1,
952 };
953
954 /* Sanitize and Sanitize Monitor/Log */
955 enum {
956         /* Sanitize */
957         NVME_SANITIZE_NO_DEALLOC        = 0x00000200,
958         NVME_SANITIZE_OIPBP             = 0x00000100,
959         NVME_SANITIZE_OWPASS_SHIFT      = 0x00000004,
960         NVME_SANITIZE_AUSE              = 0x00000008,
961         NVME_SANITIZE_ACT_CRYPTO_ERASE  = 0x00000004,
962         NVME_SANITIZE_ACT_OVERWRITE     = 0x00000003,
963         NVME_SANITIZE_ACT_BLOCK_ERASE   = 0x00000002,
964         NVME_SANITIZE_ACT_EXIT          = 0x00000001,
965
966         /* Sanitize Monitor/Log */
967         NVME_SANITIZE_LOG_DATA_LEN              = 0x0014,
968         NVME_SANITIZE_LOG_GLOBAL_DATA_ERASED    = 0x0100,
969         NVME_SANITIZE_LOG_NUM_CMPLTED_PASS_MASK = 0x00F8,
970         NVME_SANITIZE_LOG_STATUS_MASK           = 0x0007,
971         NVME_SANITIZE_LOG_NEVER_SANITIZED       = 0x0000,
972         NVME_SANITIZE_LOG_COMPLETED_SUCCESS     = 0x0001,
973         NVME_SANITIZE_LOG_IN_PROGESS            = 0x0002,
974         NVME_SANITIZE_LOG_COMPLETED_FAILED      = 0x0003,
975 };
976
977 enum {
978         /* Self-test log Validation bits */
979         NVME_SELF_TEST_VALID_NSID       = 1 << 0,
980         NVME_SELF_TEST_VALID_FLBA       = 1 << 1,
981         NVME_SELF_TEST_VALID_SCT        = 1 << 2,
982         NVME_SELF_TEST_VALID_SC         = 1 << 3,
983         NVME_SELF_TEST_REPORTS          = 20,
984 };
985
986 struct nvme_identify {
987         __u8                    opcode;
988         __u8                    flags;
989         __u16                   command_id;
990         __le32                  nsid;
991         __u64                   rsvd2[2];
992         union nvme_data_ptr     dptr;
993         __u8                    cns;
994         __u8                    rsvd3;
995         __le16                  ctrlid;
996         __u32                   rsvd11[5];
997 };
998
999 #define NVME_IDENTIFY_DATA_SIZE 4096
1000
1001 struct nvme_features {
1002         __u8                    opcode;
1003         __u8                    flags;
1004         __u16                   command_id;
1005         __le32                  nsid;
1006         __u64                   rsvd2[2];
1007         union nvme_data_ptr     dptr;
1008         __le32                  fid;
1009         __le32                  dword11;
1010         __le32                  dword12;
1011         __le32                  dword13;
1012         __le32                  dword14;
1013         __le32                  dword15;
1014 };
1015
1016 struct nvme_host_mem_buf_desc {
1017         __le64                  addr;
1018         __le32                  size;
1019         __u32                   rsvd;
1020 };
1021
1022 struct nvme_create_cq {
1023         __u8                    opcode;
1024         __u8                    flags;
1025         __u16                   command_id;
1026         __u32                   rsvd1[5];
1027         __le64                  prp1;
1028         __u64                   rsvd8;
1029         __le16                  cqid;
1030         __le16                  qsize;
1031         __le16                  cq_flags;
1032         __le16                  irq_vector;
1033         __u32                   rsvd12[4];
1034 };
1035
1036 struct nvme_create_sq {
1037         __u8                    opcode;
1038         __u8                    flags;
1039         __u16                   command_id;
1040         __u32                   rsvd1[5];
1041         __le64                  prp1;
1042         __u64                   rsvd8;
1043         __le16                  sqid;
1044         __le16                  qsize;
1045         __le16                  sq_flags;
1046         __le16                  cqid;
1047         __u32                   rsvd12[4];
1048 };
1049
1050 struct nvme_delete_queue {
1051         __u8                    opcode;
1052         __u8                    flags;
1053         __u16                   command_id;
1054         __u32                   rsvd1[9];
1055         __le16                  qid;
1056         __u16                   rsvd10;
1057         __u32                   rsvd11[5];
1058 };
1059
1060 struct nvme_abort_cmd {
1061         __u8                    opcode;
1062         __u8                    flags;
1063         __u16                   command_id;
1064         __u32                   rsvd1[9];
1065         __le16                  sqid;
1066         __u16                   cid;
1067         __u32                   rsvd11[5];
1068 };
1069
1070 struct nvme_download_firmware {
1071         __u8                    opcode;
1072         __u8                    flags;
1073         __u16                   command_id;
1074         __u32                   rsvd1[5];
1075         union nvme_data_ptr     dptr;
1076         __le32                  numd;
1077         __le32                  offset;
1078         __u32                   rsvd12[4];
1079 };
1080
1081 struct nvme_format_cmd {
1082         __u8                    opcode;
1083         __u8                    flags;
1084         __u16                   command_id;
1085         __le32                  nsid;
1086         __u64                   rsvd2[4];
1087         __le32                  cdw10;
1088         __u32                   rsvd11[5];
1089 };
1090
1091 struct nvme_get_log_page_command {
1092         __u8                    opcode;
1093         __u8                    flags;
1094         __u16                   command_id;
1095         __le32                  nsid;
1096         __u64                   rsvd2[2];
1097         union nvme_data_ptr     dptr;
1098         __u8                    lid;
1099         __u8                    lsp;
1100         __le16                  numdl;
1101         __le16                  numdu;
1102         __u16                   rsvd11;
1103         __le32                  lpol;
1104         __le32                  lpou;
1105         __u32                   rsvd14[2];
1106 };
1107
1108 struct nvme_directive_cmd {
1109         __u8                    opcode;
1110         __u8                    flags;
1111         __u16                   command_id;
1112         __le32                  nsid;
1113         __u64                   rsvd2[2];
1114         union nvme_data_ptr     dptr;
1115         __le32                  numd;
1116         __u8                    doper;
1117         __u8                    dtype;
1118         __le16                  dspec;
1119         __u8                    endir;
1120         __u8                    tdtype;
1121         __u16                   rsvd15;
1122
1123         __u32                   rsvd16[3];
1124 };
1125
1126 /* Sanitize Log Page */
1127 struct nvme_sanitize_log_page {
1128         __le16                  progress;
1129         __le16                  status;
1130         __le32                  cdw10_info;
1131         __le32                  est_ovrwrt_time;
1132         __le32                  est_blk_erase_time;
1133         __le32                  est_crypto_erase_time;
1134 };
1135
1136 /*
1137  * Fabrics subcommands.
1138  */
1139 enum nvmf_fabrics_opcode {
1140         nvme_fabrics_command            = 0x7f,
1141 };
1142
1143 enum nvmf_capsule_command {
1144         nvme_fabrics_type_property_set  = 0x00,
1145         nvme_fabrics_type_connect       = 0x01,
1146         nvme_fabrics_type_property_get  = 0x04,
1147 };
1148
1149 struct nvmf_common_command {
1150         __u8    opcode;
1151         __u8    resv1;
1152         __u16   command_id;
1153         __u8    fctype;
1154         __u8    resv2[35];
1155         __u8    ts[24];
1156 };
1157
1158 /*
1159  * The legal cntlid range a NVMe Target will provide.
1160  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1161  * Devices based on earlier specs did not have the subsystem concept;
1162  * therefore, those devices had their cntlid value set to 0 as a result.
1163  */
1164 #define NVME_CNTLID_MIN         1
1165 #define NVME_CNTLID_MAX         0xffef
1166 #define NVME_CNTLID_DYNAMIC     0xffff
1167
1168 #define MAX_DISC_LOGS   255
1169
1170 /* Discovery log page entry */
1171 struct nvmf_disc_rsp_page_entry {
1172         __u8            trtype;
1173         __u8            adrfam;
1174         __u8            subtype;
1175         __u8            treq;
1176         __le16          portid;
1177         __le16          cntlid;
1178         __le16          asqsz;
1179         __u8            resv8[22];
1180         char            trsvcid[NVMF_TRSVCID_SIZE];
1181         __u8            resv64[192];
1182         char            subnqn[NVMF_NQN_FIELD_LEN];
1183         char            traddr[NVMF_TRADDR_SIZE];
1184         union tsas {
1185                 char            common[NVMF_TSAS_SIZE];
1186                 struct rdma {
1187                         __u8    qptype;
1188                         __u8    prtype;
1189                         __u8    cms;
1190                         __u8    resv3[5];
1191                         __u16   pkey;
1192                         __u8    resv10[246];
1193                 } rdma;
1194                 struct tcp {
1195                         __u8    sectype;
1196                 } tcp;
1197         } tsas;
1198 };
1199
1200 /* Discovery log page header */
1201 struct nvmf_disc_rsp_page_hdr {
1202         __le64          genctr;
1203         __le64          numrec;
1204         __le16          recfmt;
1205         __u8            resv14[1006];
1206         struct nvmf_disc_rsp_page_entry entries[0];
1207 };
1208
1209 struct nvmf_connect_command {
1210         __u8            opcode;
1211         __u8            resv1;
1212         __u16           command_id;
1213         __u8            fctype;
1214         __u8            resv2[19];
1215         union nvme_data_ptr dptr;
1216         __le16          recfmt;
1217         __le16          qid;
1218         __le16          sqsize;
1219         __u8            cattr;
1220         __u8            resv3;
1221         __le32          kato;
1222         __u8            resv4[12];
1223 };
1224
1225 struct nvmf_connect_data {
1226         uuid_t          hostid;
1227         __le16          cntlid;
1228         char            resv4[238];
1229         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1230         char            hostnqn[NVMF_NQN_FIELD_LEN];
1231         char            resv5[256];
1232 };
1233
1234 struct nvmf_property_set_command {
1235         __u8            opcode;
1236         __u8            resv1;
1237         __u16           command_id;
1238         __u8            fctype;
1239         __u8            resv2[35];
1240         __u8            attrib;
1241         __u8            resv3[3];
1242         __le32          offset;
1243         __le64          value;
1244         __u8            resv4[8];
1245 };
1246
1247 struct nvmf_property_get_command {
1248         __u8            opcode;
1249         __u8            resv1;
1250         __u16           command_id;
1251         __u8            fctype;
1252         __u8            resv2[35];
1253         __u8            attrib;
1254         __u8            resv3[3];
1255         __le32          offset;
1256         __u8            resv4[16];
1257 };
1258
1259 struct nvme_dbbuf {
1260         __u8                    opcode;
1261         __u8                    flags;
1262         __u16                   command_id;
1263         __u32                   rsvd1[5];
1264         __le64                  prp1;
1265         __le64                  prp2;
1266         __u32                   rsvd12[6];
1267 };
1268
1269 struct streams_directive_params {
1270         __le16  msl;
1271         __le16  nssa;
1272         __le16  nsso;
1273         __u8    rsvd[10];
1274         __le32  sws;
1275         __le16  sgs;
1276         __le16  nsa;
1277         __le16  nso;
1278         __u8    rsvd2[6];
1279 };
1280
1281 struct nvme_command {
1282         union {
1283                 struct nvme_common_command common;
1284                 struct nvme_rw_command rw;
1285                 struct nvme_identify identify;
1286                 struct nvme_features features;
1287                 struct nvme_create_cq create_cq;
1288                 struct nvme_create_sq create_sq;
1289                 struct nvme_delete_queue delete_queue;
1290                 struct nvme_download_firmware dlfw;
1291                 struct nvme_format_cmd format;
1292                 struct nvme_dsm_cmd dsm;
1293                 struct nvme_write_zeroes_cmd write_zeroes;
1294                 struct nvme_abort_cmd abort;
1295                 struct nvme_get_log_page_command get_log_page;
1296                 struct nvmf_common_command fabrics;
1297                 struct nvmf_connect_command connect;
1298                 struct nvmf_property_set_command prop_set;
1299                 struct nvmf_property_get_command prop_get;
1300                 struct nvme_dbbuf dbbuf;
1301                 struct nvme_directive_cmd directive;
1302         };
1303 };
1304
1305 static inline bool nvme_is_write(struct nvme_command *cmd)
1306 {
1307         /*
1308          * What a mess...
1309          *
1310          * Why can't we simply have a Fabrics In and Fabrics out command?
1311          */
1312         if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1313                 return cmd->fabrics.fctype & 1;
1314         return cmd->common.opcode & 1;
1315 }
1316
1317 enum {
1318         /*
1319          * Generic Command Status:
1320          */
1321         NVME_SC_SUCCESS                 = 0x0,
1322         NVME_SC_INVALID_OPCODE          = 0x1,
1323         NVME_SC_INVALID_FIELD           = 0x2,
1324         NVME_SC_CMDID_CONFLICT          = 0x3,
1325         NVME_SC_DATA_XFER_ERROR         = 0x4,
1326         NVME_SC_POWER_LOSS              = 0x5,
1327         NVME_SC_INTERNAL                = 0x6,
1328         NVME_SC_ABORT_REQ               = 0x7,
1329         NVME_SC_ABORT_QUEUE             = 0x8,
1330         NVME_SC_FUSED_FAIL              = 0x9,
1331         NVME_SC_FUSED_MISSING           = 0xa,
1332         NVME_SC_INVALID_NS              = 0xb,
1333         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1334         NVME_SC_SGL_INVALID_LAST        = 0xd,
1335         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1336         NVME_SC_SGL_INVALID_DATA        = 0xf,
1337         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1338         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1339
1340         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1341         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1342
1343         NVME_SC_SANITIZE_FAILED         = 0x1C,
1344         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1345
1346         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1347
1348         NVME_SC_LBA_RANGE               = 0x80,
1349         NVME_SC_CAP_EXCEEDED            = 0x81,
1350         NVME_SC_NS_NOT_READY            = 0x82,
1351         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1352
1353         /*
1354          * Command Specific Status:
1355          */
1356         NVME_SC_CQ_INVALID              = 0x100,
1357         NVME_SC_QID_INVALID             = 0x101,
1358         NVME_SC_QUEUE_SIZE              = 0x102,
1359         NVME_SC_ABORT_LIMIT             = 0x103,
1360         NVME_SC_ABORT_MISSING           = 0x104,
1361         NVME_SC_ASYNC_LIMIT             = 0x105,
1362         NVME_SC_FIRMWARE_SLOT           = 0x106,
1363         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1364         NVME_SC_INVALID_VECTOR          = 0x108,
1365         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1366         NVME_SC_INVALID_FORMAT          = 0x10a,
1367         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1368         NVME_SC_INVALID_QUEUE           = 0x10c,
1369         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1370         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1371         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1372         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1373         NVME_SC_FW_NEEDS_RESET          = 0x111,
1374         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1375         NVME_SC_FW_ACIVATE_PROHIBITED   = 0x113,
1376         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1377         NVME_SC_NS_INSUFFICENT_CAP      = 0x115,
1378         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1379         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1380         NVME_SC_NS_IS_PRIVATE           = 0x119,
1381         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1382         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1383         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1384         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1385
1386         /*
1387          * I/O Command Set Specific - NVM commands:
1388          */
1389         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1390         NVME_SC_INVALID_PI              = 0x181,
1391         NVME_SC_READ_ONLY               = 0x182,
1392         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1393
1394         /*
1395          * I/O Command Set Specific - Fabrics commands:
1396          */
1397         NVME_SC_CONNECT_FORMAT          = 0x180,
1398         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1399         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1400         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1401         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1402
1403         NVME_SC_DISCOVERY_RESTART       = 0x190,
1404         NVME_SC_AUTH_REQUIRED           = 0x191,
1405
1406         /*
1407          * Media and Data Integrity Errors:
1408          */
1409         NVME_SC_WRITE_FAULT             = 0x280,
1410         NVME_SC_READ_ERROR              = 0x281,
1411         NVME_SC_GUARD_CHECK             = 0x282,
1412         NVME_SC_APPTAG_CHECK            = 0x283,
1413         NVME_SC_REFTAG_CHECK            = 0x284,
1414         NVME_SC_COMPARE_FAILED          = 0x285,
1415         NVME_SC_ACCESS_DENIED           = 0x286,
1416         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1417
1418         /*
1419          * Path-related Errors:
1420          */
1421         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1422         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1423         NVME_SC_ANA_TRANSITION          = 0x303,
1424
1425         NVME_SC_DNR                     = 0x4000,
1426 };
1427
1428 struct nvme_completion {
1429         /*
1430          * Used by Admin and Fabrics commands to return data:
1431          */
1432         union nvme_result {
1433                 __le16  u16;
1434                 __le32  u32;
1435                 __le64  u64;
1436         } result;
1437         __le16  sq_head;        /* how much of this queue may be reclaimed */
1438         __le16  sq_id;          /* submission queue that generated this entry */
1439         __u16   command_id;     /* of the command which completed */
1440         __le16  status;         /* did the command fail, and if so, why? */
1441 };
1442
1443 #define NVME_VS(major, minor, tertiary) \
1444         (((major) << 16) | ((minor) << 8) | (tertiary))
1445
1446 #define NVME_MAJOR(ver)         ((ver) >> 16)
1447 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1448 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1449
1450 #endif /* _LINUX_NVME_H */